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arch/arm/stm32h5: Fix hanging ADC enable call - #19929

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arch/arm/stm32h5: Fix hanging ADC enable call#19929
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liam-geotab:stm32h5-adc

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Summary

Fix an ADC issue that was seen occasionally. Increase+add a delay and "Also, clear ADRDY to ensure we are waiting for a fresh event."

The author explains:

Posix open() calls to /dev/adc# were hanging often due to the ready loop check at the end of adc_enable() never returning. According to ES0565 document, at least 4 ADC clock cycles must pass between the time we waited for calibration to end and before we can set ADEN. This will depend on what clock is set for ADC. So to ensure enough time passes, we are adding a short delay (so that even a slow clock will work). Also, we are clearing the ADRDY flag before hand to ensure we are detecting a fresh event. The delay to wait for the voltage regulator is also increased to account for extra time required in non-ideal conditions.

Impact

Delays were changed and a register write was added to avoid reading an outdated "ready" value.

The register bit is a read/write bit which is read to detect sample "ready", and written with a 1 to clear it. It is cleared at the end, but it's defensively being cleared in case of an existing value.

Testing

I have validated this patch in isolation on the custom board by measuring a depleting a capacitor and the voltage source upstream of a diode before and after removing the voltage source.

Custom STM32H5 board with 12 ADC channels. config with:

CONFIG_ADC=y
CONFIG_ADC_FIFOSIZE=16
CONFIG_STM32_ADC1=y
CONFIG_EXAMPLES_ADC=y
CONFIG_EXAMPLES_ADC_GROUPSIZE=12
CONFIG_EXAMPLES_ADC_SWTRIG=y

Grepping the two channels of interest:

4: channel: 4 value: 495
4: channel: 4 value: 495
4: channel: 4 value: 495
...
4: channel: 4 value: 21
4: channel: 4 value: 21
4: channel: 4 value: 21
11: channel: 14 value: 2357
11: channel: 14 value: 2357
11: channel: 14 value: 2359
...
11: channel: 14 value: 522
11: channel: 14 value: 520
11: channel: 14 value: 518

Posix open() calls to /dev/adc# were hanging often due
to the ready loop check at the end of adc_enable() never
returning.  According to ES0565 document, at least 4 ADC
clock cycles must pass between the time we waited for
calibration to end and before we can set ADEN. This will
depend on what clock is set for ADC. So to ensure enough
time passes, we are adding a short delay (so that even a
slow clock will work).  Also, we are clearing the ADRDY
flag before hand to ensure we are detecting a fresh event.
The delay to wait for the voltage regulator is also
increased to account for extra time required in
non-ideal conditions.

Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
@github-actions github-actions Bot added Arch: arm Issues related to ARM (32-bit) architecture Size: S The size of the change in this PR is small labels Aug 21, 2026
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MemBrowse Memory Report

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Arch: arm Issues related to ARM (32-bit) architecture Size: S The size of the change in this PR is small

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3 participants